Please use this identifier to cite or link to this item:
http://hdl.handle.net/10603/420630
Title: | Design and implementation of core micro architecture based on risc v isa |
Researcher: | Bora, Satyajit |
Guide(s): | Paily, Roy P |
Keywords: | Engineering Engineering and Technology Engineering Electrical and Electronic |
University: | Indian Institute of Technology Guwahati |
Completed Date: | 2022 |
Abstract: | The demand for low power and low cost CPUs is increasing due to cloud computing and IoT endpoint applications In this work three 32 bit core micro architectures are proposed to meet the requirements of modern world devices The cores are targeted to three different applications low power data centric IoT devices and high security The cores are based on RISC V ISA with the support of some new custom instructions those help in enhancing the core performance The low power core is a four stage... |
Pagination: | Not Available |
URI: | http://hdl.handle.net/10603/420630 |
Appears in Departments: | DEPARTMENT OF ELECTRONICS AND ELECTRICAL ENGINEERING |
Files in This Item:
File | Description | Size | Format | |
---|---|---|---|---|
01_fulltext.pdf | Attached File | 7.24 MB | Adobe PDF | View/Open |
04_abstract.pdf | 110.5 kB | Adobe PDF | View/Open | |
80_recommendation.pdf | 692.33 kB | Adobe PDF | View/Open |
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