Shodhganga : a reservoir of Indian theses @ INFLIBNET
The Shodhganga@INFLIBNET Centre provides a platform for research students to deposit their Ph.D. theses and make it available to the entire scholarly community in open access.
Please use this identifier to cite or link to this item:
http://hdl.handle.net/10603/420600
| Title: | Designing data aware network on chip for performance |
| Researcher: | Das, Abhijit |
| Guide(s): | Jose, John |
| Keywords: | Computer Science Computer Science Artificial Intelligence Engineering and Technology |
| University: | Indian Institute of Technology Guwahati |
| Completed Date: | 2021 |
| Abstract: | We are now in an era where data drives everything and the demand for information processing is increasing exponentially This increasing demand is driving a parallel increase in the number of processing cores in Tiled Chip Multi Processors TCMPs It is indeed visible in the industry with Intel Xeon Phi AMD EPYC and Ampere Altra processors featuring up to 128 cores in their TCMPs As the number of cores continues to increase in modern TCMPs on chip communication plays a pivotal role in dete |
| Pagination: | Not Available |
| URI: | http://hdl.handle.net/10603/420600 |
| Appears in Departments: | Department of Computer Science and Engineering |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| 01_fulltext.pdf | Attached File | 2.8 MB | Adobe PDF | View/Open |
| 04_abstract.pdf | 113.94 kB | Adobe PDF | View/Open | |
| 80_recommendation.pdf | 236.68 kB | Adobe PDF | View/Open |
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