Please use this identifier to cite or link to this item:
http://hdl.handle.net/10603/420443
Title: | Performance enhancement techniques for low voltage bulk driven circuits |
Researcher: | Veldandi, Harikrishna |
Guide(s): | Ahamed, Shaik Rafi |
Keywords: | Engineering Engineering and Technology Engineering Electrical and Electronic |
University: | Indian Institute of Technology Guwahati |
Completed Date: | 2019 |
Abstract: | In advanced CMOS process the device performance characteristics gets affected by changes in the number of fingers due to shallow trench isolation effect which in turn changes the circuit performance A systematic design procedure based on gm ID gmb ID and normalized current ID W characteristics is presented This methodology is used to evaluate the device geometry by considering the number of fingers which meets the desired specifications A PVT intensive bulk driven OTA with improved gain |
Pagination: | Not Available |
URI: | http://hdl.handle.net/10603/420443 |
Appears in Departments: | DEPARTMENT OF ELECTRONICS AND ELECTRICAL ENGINEERING |
Files in This Item:
File | Description | Size | Format | |
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01_fulltext.pdf | Attached File | 3.73 MB | Adobe PDF | View/Open |
04_abstract.pdf | 115.93 kB | Adobe PDF | View/Open | |
80_recommendation.pdf | 128.15 kB | Adobe PDF | View/Open |
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