Investigation on low power and high Stable cntfet based sram

Abstract

In a sub-micron range of design, the CMOS circuits are more sensitive to process parameters variation, which increases the static power consumption. These process parameters variation easily affect the small size transistors used in area constrained circuits such as Static Random Access Memory (SRAM) cells. The nanometer SRAM design faces numerous design challenges like leakage of power, low noise margin and loss in parametric yield. To deal with these design challenges, it is essential to focus on increasing the SRAM cell stability and leakage power reduction.There are several low-power circuit-design methods to achieve low power SRAM design. These biasing techniques such as separate supply to source and substrate; and dynamically decrease power supply. But these biasing techniques and supply voltage reduction methods increase the failure rate of the stored bit. In general, the stored bit in the SRAM cell faces the following failure mechanisms Read, write and hold failure and access time failure due to process parameter variations. Cosmic and alpha particles from die packaging cause soft errors. Data retention fault due to source biasing for leakage power reduction. Reduction of supply voltage to achieve low power design cause poor data stabilityIn this thesis, CNTFET SRAM cells proposed and designed to realise low power consumption and high stability. A 6T CNTFET SRAM cell is designed and its power consumption and noise margin are observed for CNTFET parameter variations. The 6T CNTFET SRAM cell is optimised by selecting the best values of CNTFET parameters to achieve low power and high stable SRAM design. newline