Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/414326
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dc.coverage.spatialMachine learning assisted methodology for online testing of processor pipeline
dc.date.accessioned2022-10-25T05:18:42Z-
dc.date.available2022-10-25T05:18:42Z-
dc.identifier.urihttp://hdl.handle.net/10603/414326-
dc.description.abstractDesign bug detection is an important research area for processor manufacturers. Processor verification happens in three different stages during its development cycle, namely, pre-silicon verification, post-silicon validation and online testing (runtime verification). In spite of the rigorous verification carried out by the industry in both pre-silicon and post-silicon stages, some of the bugs still escape and enter into the manufactured products. Examples of well-known design bugs in real-word processors include Pentium FDIV bug, TLB bug, TSX bug, Skylake bug, Spectre and Meltdown bugs. Based on the severity of the bug, these design bugs have a huge impact both from manufacturer and user point of view. Hence, there is a need to detect these escaped design bugs in real-world processors which is possible through online testing. The focus of this research is to detect the functional bugs in a processor s pipeline, branch prediction and arithmetic units through online testing. The challenges of online testing are limited observability and controllability of a chip. In this research, we address these challenges by tracking the overall behaviour of a processor from a high-level perspective by leveraging the Performance Monitoring Counters (PMCs) available on processors to monitor the processor s microarchitectural events when an application is executed. We establish the correlation between the PMC events and the occurrence of bugs. Based on this correlation, we learn the bug signature in terms of PMC events and use machine learning algorithms to build models that predict the occurrence of bugs in the pipeline and branch prediction units of a processor. The major contribution of this research is the proposal of a generic methodology for online detection of functional bugs in a processor using machine learning. In this direction, our contributions are detection of pipeline unit and branch prediction unit bugs for x86 processor, and detection of scalar iv unit pipeline bugs for AMD Southern Islands processor newline newline newline
dc.format.extentp.196-209
dc.languageEnglish
dc.relationp.196-209
dc.rightsuniversity
dc.titleMachine learning assisted methodology for online testing of processor pipeline
dc.title.alternative
dc.creator.researcherPadma, J
dc.subject.keywordEngineering and Technology
dc.subject.keywordComputer Science
dc.subject.keywordComputer Science Information Systems
dc.subject.keywordprocessor pipeline
dc.subject.keywordDesign bug detection
dc.subject.keywordMachine learning
dc.description.note
dc.contributor.guideRanjani parthasarathi
dc.publisher.placeChennai
dc.publisher.universityAnna University
dc.publisher.institutionFaculty of Information and Communication Engineering
dc.date.registered
dc.date.completed2022
dc.date.awarded2022
dc.format.dimensionsxxiii, 210p
dc.format.accompanyingmaterialNone
dc.source.universityUniversity
dc.type.degreePh.D.
Appears in Departments:Faculty of Information and Communication Engineering

Files in This Item:
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01_title.pdfAttached File29.22 kBAdobe PDFView/Open
02_prelim pages.pdf1.66 MBAdobe PDFView/Open
03_contents.pdf634.42 kBAdobe PDFView/Open
04_abstracts.pdf187.06 kBAdobe PDFView/Open
05_chapter 1.pdf577.97 kBAdobe PDFView/Open
06_chapter 2.pdf361.71 kBAdobe PDFView/Open
07_chapter 3.pdf1.22 MBAdobe PDFView/Open
08_chapter 4.pdf568.48 kBAdobe PDFView/Open
09_chapter 5.pdf672.86 kBAdobe PDFView/Open
10_chapter 6.pdf362.29 kBAdobe PDFView/Open
11_annexures.pdf504.83 kBAdobe PDFView/Open
80_recommendation.pdf373.24 kBAdobe PDFView/Open


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