Please use this identifier to cite or link to this item:
http://hdl.handle.net/10603/414326
Title: | Machine learning assisted methodology for online testing of processor pipeline |
Researcher: | Padma, J |
Guide(s): | Ranjani parthasarathi |
Keywords: | Engineering and Technology Computer Science Computer Science Information Systems processor pipeline Design bug detection Machine learning |
University: | Anna University |
Completed Date: | 2022 |
Abstract: | Design bug detection is an important research area for processor manufacturers. Processor verification happens in three different stages during its development cycle, namely, pre-silicon verification, post-silicon validation and online testing (runtime verification). In spite of the rigorous verification carried out by the industry in both pre-silicon and post-silicon stages, some of the bugs still escape and enter into the manufactured products. Examples of well-known design bugs in real-word processors include Pentium FDIV bug, TLB bug, TSX bug, Skylake bug, Spectre and Meltdown bugs. Based on the severity of the bug, these design bugs have a huge impact both from manufacturer and user point of view. Hence, there is a need to detect these escaped design bugs in real-world processors which is possible through online testing. The focus of this research is to detect the functional bugs in a processor s pipeline, branch prediction and arithmetic units through online testing. The challenges of online testing are limited observability and controllability of a chip. In this research, we address these challenges by tracking the overall behaviour of a processor from a high-level perspective by leveraging the Performance Monitoring Counters (PMCs) available on processors to monitor the processor s microarchitectural events when an application is executed. We establish the correlation between the PMC events and the occurrence of bugs. Based on this correlation, we learn the bug signature in terms of PMC events and use machine learning algorithms to build models that predict the occurrence of bugs in the pipeline and branch prediction units of a processor. The major contribution of this research is the proposal of a generic methodology for online detection of functional bugs in a processor using machine learning. In this direction, our contributions are detection of pipeline unit and branch prediction unit bugs for x86 processor, and detection of scalar iv unit pipeline bugs for AMD Southern Islands processor newline newline newline |
Pagination: | p.196-209 |
URI: | http://hdl.handle.net/10603/414326 |
Appears in Departments: | Faculty of Information and Communication Engineering |
Files in This Item:
File | Description | Size | Format | |
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01_title.pdf | Attached File | 29.22 kB | Adobe PDF | View/Open |
02_prelim pages.pdf | 1.66 MB | Adobe PDF | View/Open | |
03_contents.pdf | 634.42 kB | Adobe PDF | View/Open | |
04_abstracts.pdf | 187.06 kB | Adobe PDF | View/Open | |
05_chapter 1.pdf | 577.97 kB | Adobe PDF | View/Open | |
06_chapter 2.pdf | 361.71 kB | Adobe PDF | View/Open | |
07_chapter 3.pdf | 1.22 MB | Adobe PDF | View/Open | |
08_chapter 4.pdf | 568.48 kB | Adobe PDF | View/Open | |
09_chapter 5.pdf | 672.86 kB | Adobe PDF | View/Open | |
10_chapter 6.pdf | 362.29 kB | Adobe PDF | View/Open | |
11_annexures.pdf | 504.83 kB | Adobe PDF | View/Open | |
80_recommendation.pdf | 373.24 kB | Adobe PDF | View/Open |
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