Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/408426
Title: Determinization Clock Reduction and Experimental Analysis of Timed Systems
Researcher: P Vijay Suman
Guide(s): Paritosh K. Pandya
Keywords: Engineering and Technology
Computer Science
Computer Science Information Systems
University: Tata Institute of Fundamental Research
Completed Date: 2010
Abstract: newline
Pagination: 
URI: http://hdl.handle.net/10603/408426
Appears in Departments:School of Technology and Computer Science (STCS)

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01_title.pdfAttached File16.88 kBAdobe PDFView/Open
02_declaration.pdf32.79 kBAdobe PDFView/Open
05_contents.pdf47.5 kBAdobe PDFView/Open
06_list of table & figures.pdf75.45 kBAdobe PDFView/Open
08_chapter 1.pdf151.13 kBAdobe PDFView/Open
09_chapter 2.pdf314.54 kBAdobe PDFView/Open
10_chapter 3.pdf201.72 kBAdobe PDFView/Open
11_chapter 4.pdf299.63 kBAdobe PDFView/Open
12_chapter 5.pdf186.12 kBAdobe PDFView/Open
13_chapter 6.pdf260.4 kBAdobe PDFView/Open
14_chapter 7.pdf70.12 kBAdobe PDFView/Open
15_bibliography.pdf80.45 kBAdobe PDFView/Open
16_appendix.pdf79.46 kBAdobe PDFView/Open
17_synopsis.pdf140.2 kBAdobe PDFView/Open
18_list of publications.pdf34.31 kBAdobe PDFView/Open
80_recommendation.pdf208.14 kBAdobe PDFView/Open
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