An investigation on macro and micro Architectures for network on chip

Abstract

As the technology scales down more processors or Processing newlineElements PEs are integrated in the same die and such technology is called as newlineMultiprocessor System on Chip MPSoC In the earlier MPSoCs bus newlinecommunication architecture is used for communication of processors or PEs newlinewith each other However this traditional bus communication architecture is newlinenot suitable for more complex MPSoCs because of its limited scalability and newlinereliability To provide better communication architecture for complex newlineMPSoCs new communication architecture Network on Chip NoC emerged newlineas alternate for bus NoC uses the concepts and design methodologies adopted newlinefrom computer network Silicon implementation of networks requires newlinedifferent perspectives because network architectures and protocols have to newlinedeal with the advantages and limitations of the silicon fabric These newlinecharacteristics require new methodologies for both on chip router designs as newlinewell as routing algorithm designs The research works on NoCs have multi newlinedimension to solve different issues and they are arranged in two groups newlinenamed as Macro and Micro architectures Macro architectural choices aim to newlinemerge interconnection architecture with remaining systems and Microarchitectural newlineaims at innovations within NoC components newline