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http://hdl.handle.net/10603/406428
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DC Field | Value | Language |
---|---|---|
dc.coverage.spatial | ||
dc.date.accessioned | 2022-09-20T05:46:48Z | - |
dc.date.available | 2022-09-20T05:46:48Z | - |
dc.identifier.uri | http://hdl.handle.net/10603/406428 | - |
dc.description.abstract | Available newline | |
dc.format.extent | xvii, 142p. | |
dc.language | English | |
dc.relation | ||
dc.rights | university | |
dc.title | Methodologies for Optimization of Digital Circuits using Cyclic Combinational Technique and Hybrid CMOS Logic Style | |
dc.title.alternative | ||
dc.creator.researcher | Kumar, Vinay | |
dc.subject.keyword | Digital electronics | |
dc.subject.keyword | Digital integrated circuits | |
dc.subject.keyword | Electronics | |
dc.subject.keyword | Engineering | |
dc.subject.keyword | Engineering and Technology | |
dc.subject.keyword | Engineering Electrical and Electronic | |
dc.subject.keyword | Logic circuits | |
dc.description.note | ||
dc.contributor.guide | Dandapat, Anup | |
dc.publisher.place | Shillong | |
dc.publisher.university | National Institute of Technology (NIT) Meghalaya | |
dc.publisher.institution | ELECTRONICS and COMMUNICATION ENGINEERING | |
dc.date.registered | 2013 | |
dc.date.completed | 2017 | |
dc.date.awarded | 2017 | |
dc.format.dimensions | ||
dc.format.accompanyingmaterial | None | |
dc.source.university | University | |
dc.type.degree | Ph.D. | |
Appears in Departments: | ELECTRONICS & COMMUNICATION ENGINEERING |
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