Please use this identifier to cite or link to this item:
http://hdl.handle.net/10603/404367
Title: | Tunnel FET based energy efficient circuit design with enhanced hardware security |
Researcher: | Aditya, Japa |
Guide(s): | Majumder, Manoj K and Sahoo, Subhendu K |
Keywords: | Hardware obfuscation Hardware security Physically unclonable function (PUF) Side channel analysis True random number generator (TRNG) Tunnel FET (TFET) |
University: | Dr. Shyama Prasad Mukherjee International Institute of Information Technology Naya Raipur |
Completed Date: | 2021 |
Abstract: | Abstract available as PDF newline |
Pagination: | 188 |
URI: | http://hdl.handle.net/10603/404367 |
Appears in Departments: | Electronics and Communication Engineering |
Files in This Item:
File | Description | Size | Format | |
---|---|---|---|---|
01_title.pdf | Attached File | 124.55 kB | Adobe PDF | View/Open |
02_declaration.pdf | 112.61 kB | Adobe PDF | View/Open | |
03_certificate.pdf | 857.56 kB | Adobe PDF | View/Open | |
04_acknowledgemwnt.pdf | 457.95 kB | Adobe PDF | View/Open | |
05_contents.pdf | 692.82 kB | Adobe PDF | View/Open | |
06_list of graph and tables.pdf | 2.08 MB | Adobe PDF | View/Open | |
07_abstract.pdf | 715.43 kB | Adobe PDF | View/Open | |
08_chapter 1.pdf | 4.99 MB | Adobe PDF | View/Open | |
09_chapter 2.pdf | 10.79 MB | Adobe PDF | View/Open | |
10_chapter 3.pdf | 8.51 MB | Adobe PDF | View/Open | |
11_chapter 4.pdf | 6.25 MB | Adobe PDF | View/Open | |
12_chapter 5.pdf | 30.26 MB | Adobe PDF | View/Open | |
13_chapter 6.pdf | 5.88 MB | Adobe PDF | View/Open | |
14_references.pdf | 5.4 MB | Adobe PDF | View/Open |
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