Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/404367
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DC FieldValueLanguage
dc.coverage.spatial
dc.date.accessioned2022-09-12T06:17:42Z-
dc.date.available2022-09-12T06:17:42Z-
dc.identifier.urihttp://hdl.handle.net/10603/404367-
dc.description.abstractAbstract available as PDF newline
dc.format.extent188
dc.languageEnglish
dc.relation150
dc.rightsuniversity
dc.titleTunnel FET based energy efficient circuit design with enhanced hardware security
dc.title.alternative
dc.creator.researcherAditya, Japa
dc.subject.keywordHardware obfuscation
dc.subject.keywordHardware security
dc.subject.keywordPhysically unclonable function (PUF)
dc.subject.keywordSide channel analysis
dc.subject.keywordTrue random number generator (TRNG)
dc.subject.keywordTunnel FET (TFET)
dc.description.note
dc.contributor.guideMajumder, Manoj K and Sahoo, Subhendu K
dc.publisher.placeRaipur
dc.publisher.universityDr. Shyama Prasad Mukherjee International Institute of Information Technology Naya Raipur
dc.publisher.institutionElectronics and Communication Engineering
dc.date.registered2016
dc.date.completed2021
dc.date.awarded2021
dc.format.dimensions
dc.format.accompanyingmaterialNone
dc.source.universityUniversity
dc.type.degreePh.D.
Appears in Departments:Electronics and Communication Engineering

Files in This Item:
File Description SizeFormat 
01_title.pdfAttached File124.55 kBAdobe PDFView/Open
02_declaration.pdf112.61 kBAdobe PDFView/Open
03_certificate.pdf857.56 kBAdobe PDFView/Open
04_acknowledgemwnt.pdf457.95 kBAdobe PDFView/Open
05_contents.pdf692.82 kBAdobe PDFView/Open
06_list of graph and tables.pdf2.08 MBAdobe PDFView/Open
07_abstract.pdf715.43 kBAdobe PDFView/Open
08_chapter 1.pdf4.99 MBAdobe PDFView/Open
09_chapter 2.pdf10.79 MBAdobe PDFView/Open
10_chapter 3.pdf8.51 MBAdobe PDFView/Open
11_chapter 4.pdf6.25 MBAdobe PDFView/Open
12_chapter 5.pdf30.26 MBAdobe PDFView/Open
13_chapter 6.pdf5.88 MBAdobe PDFView/Open
14_references.pdf5.4 MBAdobe PDFView/Open


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