1. Shodhganga@INFLIBNET
  2. Dr. Shyama Prasad Mukherjee International Institute of Information Technology Naya Raipur
  3. Electronics and Communication Engineering
Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/404367
Title: Tunnel FET based energy efficient circuit design with enhanced hardware security
Researcher: Aditya, Japa
Guide(s): Majumder, Manoj K and Sahoo, Subhendu K
Keywords: Hardware obfuscation
Hardware security
Physically unclonable function (PUF)
Side channel analysis
True random number generator (TRNG)
Tunnel FET (TFET)
University: Dr. Shyama Prasad Mukherjee International Institute of Information Technology Naya Raipur
Completed Date: 2021
Abstract: Abstract available as PDF newline
Pagination: 188
URI: http://hdl.handle.net/10603/404367
Appears in Departments:Electronics and Communication Engineering

Files in This Item:
File Description SizeFormat 
01_title.pdfAttached File124.55 kBAdobe PDFView/Open
02_declaration.pdf112.61 kBAdobe PDFView/Open
03_certificate.pdf857.56 kBAdobe PDFView/Open
04_acknowledgemwnt.pdf457.95 kBAdobe PDFView/Open
05_contents.pdf692.82 kBAdobe PDFView/Open
06_list of graph and tables.pdf2.08 MBAdobe PDFView/Open
07_abstract.pdf715.43 kBAdobe PDFView/Open
08_chapter 1.pdf4.99 MBAdobe PDFView/Open
09_chapter 2.pdf10.79 MBAdobe PDFView/Open
10_chapter 3.pdf8.51 MBAdobe PDFView/Open
11_chapter 4.pdf6.25 MBAdobe PDFView/Open
12_chapter 5.pdf30.26 MBAdobe PDFView/Open
13_chapter 6.pdf5.88 MBAdobe PDFView/Open
14_references.pdf5.4 MBAdobe PDFView/Open
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