Design of power efficient CDR circuit constituents for serial data communication

Abstract

The Clock and Data Recovery Circuit (CDR) is a key block for serial-link I/O transceiver design. To accomplish a performance efficient CDR, several attempts are done in literature to investigate its constituents such as phase/frequency detector(PFD), charge pump (CP), voltage-controlled oscillator (VCO) and decision circuit, where we have outlined several existing issues like dead/blind zone, current mismatch and lock-in time, achieving higher frequency with better tuning range and area overhead respectively. To address these, novel designs of PFD-CP, VCO and decision circuit are tendered in this thesis for possible configuration of a speed-power-area efficient and robust CDR circuit for its application in onchip serial data communication. The new PFD-CP circuit uses no reset path to in-turn improve the speed and dead zone/blind zone. This design significantly reduces the phase noise, output noise and switching time and is well tested under extreme process corners. A novel hybrid ring VCO is reported cascading basic CMOS inverter and current starved inverter placed alternatively to achieve ultra-low power, higher oscillation frequency with wide tuning range and low gate count. The oscillation frequency is estimated in terms of a mathematical model along with an analysis justifying the better tuning range. Robustness and reliability are justified by Monte Carlo analysis at different process corners. To synchronize the received signal in a feed forward way to remove the needless jitter-noise and to improve the SNR, a passive element free, power-area efficient high data speed decision circuit is implemented by cascading a preamplifier, master-slave D-FF and an output buffer. The MS-DFF is built by a new dynamic current mode D-latch, being the heart of this retimer circuit to improve the propagation delay and better voltage swing. All the simulations are carried out for 90nm CMOS technology at a power supply of 1.2 Volt using Cadence Virtuoso platform.