1. Shodhganga@INFLIBNET
  2. Indian Institute of Technology Madras
  3. Electrical Engineering
Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/400227
Title: Hardware efficient algorithms and architectures for Convolutional neural networks
Researcher: YASHRAJSINH RAGHUVIRSINH PARMAR
Guide(s): K, Sridharan
Keywords: Engineering
Engineering and Technology
Engineering Electrical and Electronic
University: Indian Institute of Technology Madras
Completed Date: 2021
Abstract: newline AVAILABLE
Pagination: xvii, 168p
URI: http://hdl.handle.net/10603/400227
Appears in Departments:Electrical Engineering

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01_title.pdfAttached File66.08 kBAdobe PDFView/Open
03_certificate.pdf40 kBAdobe PDFView/Open
04_acknowledgement.pdf59.57 kBAdobe PDFView/Open
05_content.pdf48.51 kBAdobe PDFView/Open
06_list of graph and table.pdf171.74 kBAdobe PDFView/Open
07_abstract.pdf41.01 kBAdobe PDFView/Open
08_chapter 1.pdf105.12 kBAdobe PDFView/Open
09_chapter 2.pdf387.43 kBAdobe PDFView/Open
10_chapter 3.pdf307.43 kBAdobe PDFView/Open
11_chapter 4.pdf552.16 kBAdobe PDFView/Open
12_chapter 5.pdf823.13 kBAdobe PDFView/Open
13_chapter 6.pdf824.75 kBAdobe PDFView/Open
14_chapter 7.pdf100.38 kBAdobe PDFView/Open
15_annexure.pdf818.99 kBAdobe PDFView/Open
16_bibliography.pdf106.9 kBAdobe PDFView/Open
17_abbreviations and notations.pdf40.82 kBAdobe PDFView/Open
80_recommendation.pdf168.95 kBAdobe PDFView/Open
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