Design implementation and Performance evaluation of network On chip communication link router

Abstract

In today s mobile and communication world Router plays a newlinesignificant role to select classify and forward the data from source node to newlinedestination node or intermediate nodes in this environment The size or area newlineof the router design is very important while considering the device it is newlinepossible to integrate hundreds of billions of transistors on a single chip newlinewhich will allow for the integration of hundreds or even thousands of newlineprocessor cores a multi many core architecture on a single die along with newlinethe interconnect infrastructure and memory In a multi many core newlinearchitecture the interconnect occupies a large amount of the on chip area newlinea large amount of gates that otherwise might have been deployed for newlineincreasing the number and the complexity of the computational resources now newlineneed to be deployed for designing the communication infrastructure NoCs newlinehave been studied on chip communication architectures for design time newlineparameterized application specific static multi many core systems An newlineapplication specific NoC defined as a design time parameterized architecture newlinewith a fixed routing scheme a fixed number of allowed virtual connections at newlineeach output port or a fixed application mapping instance NoCs as a systemon newlinechip communication architecture, its different design methodologies and newlinekey research problems were discussed in literature survey newline newline newline