Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/397589
Title: Design of Hardware implementation for image contrast enhancement using arty seven FPGA
Researcher: Madhu Raghaveendra M
Guide(s): Lakshmaiah M V
Keywords: Physical Sciences
Physics
Physics Mathematical
University: Sri Krishnadevaraya University
Completed Date: 2020
Abstract: newlineImplementation for image contrast enhancement
Pagination: 
URI: http://hdl.handle.net/10603/397589
Appears in Departments:Department of Electronics

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01_title.pdf.pdfAttached File13.27 kBAdobe PDFView/Open
02_declaration.pdf.pdf108.71 kBAdobe PDFView/Open
03_certificate.pdf.pdf305.12 kBAdobe PDFView/Open
04_acknowledgements.pdf.pdf117.34 kBAdobe PDFView/Open
05_contents.pdf.pdf41.09 kBAdobe PDFView/Open
06_list of figures.pdf.pdf122.3 kBAdobe PDFView/Open
07_chapter 1.pdf.pdf1.23 MBAdobe PDFView/Open
08_chapter 2.pdf.pdf246.74 kBAdobe PDFView/Open
09_chapter 3.pdf.pdf1.44 MBAdobe PDFView/Open
10_chapter 4.pdf.pdf1.45 MBAdobe PDFView/Open
11_chapter 5.pdf.pdf1.69 MBAdobe PDFView/Open
12_references.pdf.pdf326.23 kBAdobe PDFView/Open
80_recommendation.pdf9.04 kBAdobe PDFView/Open
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