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http://hdl.handle.net/10603/396268
Title: | Design and Simulation of Single Electron Transistor Based High Performance Computing System at Room Temperature |
Researcher: | Patel, Rashmit |
Guide(s): | Parekh, Rutu and Agrawal, Yash |
Keywords: | Engineering and Technology Engineering Engineering Electrical and Electronic Integrated circuits--Very large scale integration Transputers Very high speed integrated circuits Systolic array circuits Analog CMOS integrated circuits Nanoelectronics Heterogeneous computing |
University: | Dhirubhai Ambani Institute of Information and Communication Technology (DA-IICT) |
Completed Date: | 2021 |
Abstract: | quotThe VLSI technology has seamlessly grown over the years, that yields high-performance, low-power and high-density devices. Over the several decades,the performance of existing complementary metal-oxide semiconductor (CMOS) technology has been constantly improved by scaling of the transistors size. The scaling and heterogeneous 3D integration aids in achieving high-density logic. However, the performance of nanometer scale CMOS based designs is limited due to the short-channel effect, leakage current and process variations. There is a trade-off between speed and power consumption that significantly affects the performance of complex designs like computing devices. The nanoelectronics devices having the capabilities of heterogeneous 3D integration and functional integration with existing technologies serves potential solutions to future silicon technology challenges. These devices can overcome the aforesaid problems and escalates the capabilities of electronics devices in terms of speed, power, density, newlinesize and volume. newline newlineThe single electron transistor (SET) is a promising and elegant nano-device which possesses several convincing features such as low energy consumption, newlineefficient operational at room temperature, high switching speed, sustainable with scaling and reduced operating potentials to compete or outperform conventional CMOS technology. The SET can be used as basic element in either individual circuit or hybrid circuit with existing CMOS technology. The survey of individual SET based designs shows that these are at smaller block level with improper SET parameters, operating temperature, interconnect parasitics, etc. The bottleneck with SET based designs having thousands of gates, is unavailability of either dedicated electronic design automation (EDA) tool or standard component library or synthesizer. This research gap is accomplished by proposed SET based computing system with consideration of realistic SET parameters and interconnects parasitics at room temperature operation. newline newlineThe SET based computing... |
Pagination: | xvii, 122 p. |
URI: | http://hdl.handle.net/10603/396268 |
Appears in Departments: | Department of Information and Communication Technology |
Files in This Item:
File | Description | Size | Format | |
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01_title.pdf | Attached File | 58.66 kB | Adobe PDF | View/Open |
02_declaration and certificate.pdf | 74.81 kB | Adobe PDF | View/Open | |
03_acknowledgments.pdf | 55.7 kB | Adobe PDF | View/Open | |
04_contents.pdf | 60.93 kB | Adobe PDF | View/Open | |
05_abstract.pdf | 78.53 kB | Adobe PDF | View/Open | |
06_list of symbols, abbreviation, tables and figures.pdf | 302.55 kB | Adobe PDF | View/Open | |
07_chapter 1.pdf | 148.31 kB | Adobe PDF | View/Open | |
09_chapter 3.pdf | 830.5 kB | Adobe PDF | View/Open | |
10_chapter 4.pdf | 153.71 kB | Adobe PDF | View/Open | |
11_chapter 5.pdf | 256.93 kB | Adobe PDF | View/Open | |
12_chapter 6.pdf | 62.14 kB | Adobe PDF | View/Open | |
13_publications.pdf | 75.32 kB | Adobe PDF | View/Open | |
14_appendix.pdf | 132.48 kB | Adobe PDF | View/Open | |
18_bibliography.pdf | 118.06 kB | Adobe PDF | View/Open | |
80_recommendation.pdf | 74.05 kB | Adobe PDF | View/Open | |
8_chapter 2.pdf | 410.3 kB | Adobe PDF | View/Open |
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