1. Shodhganga@INFLIBNET
  2. Kalasalingam University
  3. Department of Electronics and Communication Engineering
Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/395939
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DC FieldValueLanguage
dc.coverage.spatial
dc.date.accessioned2022-07-27T09:05:23Z-
dc.date.available2022-07-27T09:05:23Z-
dc.identifier.urihttp://hdl.handle.net/10603/395939-
dc.description.abstractnewline
dc.format.extent
dc.languageEnglish
dc.relation
dc.rightsuniversity
dc.titleOptimization Algorithms for Thermal Aware Partitioning and Floorplanning of 3D ICs
dc.title.alternative
dc.creator.researcherJeya Prakash K
dc.subject.keywordEngineering
dc.subject.keywordEngineering and Technology
dc.subject.keywordEngineering Electrical and Electronic
dc.description.note
dc.contributor.guideP Sivakumar
dc.publisher.placeVirudhunagar
dc.publisher.universityKalasalingam University
dc.publisher.institutionDepartment of Electronics and Communication Engineering
dc.date.registered2014
dc.date.completed2022
dc.date.awarded2022
dc.format.dimensions
dc.format.accompanyingmaterialDVD
dc.source.universityUniversity
dc.type.degreePh.D.
Appears in Departments:Department of Electronics and Communication Engineering

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201408223_jeya prakash k_thesis_final.pdfAttached File3.51 MBAdobe PDFView/Open
80_recommendation.pdf165.12 kBAdobe PDFView/Open
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