Design and Implementation of Traffic Congestion Aware Network on Chip for Automotive System on Chips

Abstract

Moving towards an advanced driver assisting system (ADAS) and autonomous driving, the larger amount of computing power and efficient communication infrastructure are required for the high performance. Such move increases the demand of centralized high computing capabilities in the modern cars to have more real time data. The multi core system on chip (MCSoC) platform has replaced the large number of distributed electronics control units into centralized multicore system due to resolution of semiconductor in automotive industry and the advancement of very large scale integration (VLSI) system design techniques. Similarly, the number of the distributed electronic control units (ECU) used in modern car to satisfy the demand on the safety and comfort features causes for the communication network complexity in ECUs and also inefficient in delivering high performance. Networked ECU s complexity is reduced in the multi-core system on chip (MCSoC or SOC) domain controller where several ECUs with various functionalities are integrated as a single commanding MCSoC. Generally, Modern vehicle are equipped with MCSoC as the advanced sensors such as 4D lidar on chip, radar on chip and camera on chip which further demands more computing power with energy efficient interconnect capabilities. In addition to this in today s vehicle, monitoring the vehicle status and processing the safety critical conditions have turned as the necessary features. This creates the demand of deploying MCSoC within the vehicles to meet the safety standards. In particular, vehicle monitoring and safety related SoC run even after shut down the engine of the vehicle such as immobilizer system, Telematics, child occupant monitoring, diagnosis over internet, status monitoring application, and local artificial intelligent assistance etc. These MCSoC can drain the battery power of the vehicle and may reduce the power level.