Certain investigations on performance analysis of VLSI implementation of area efficient multiplier accumulator unit for fir filter

Abstract

The increase in demand of portable devices makes Low power device design and it becomes an important field of research Power dissipation is one of the fundamental design objectives in integrated circuit after speed Design of low area delay and power forms the largest systems in VLSI system design These three parameters I e power area and speed are always traded off However area and speed are usually conflicting constraints so that improving speed results mostly in larger areas newlineThe addition and multiplication of two binary numbers are the fundamental and most frequently used arithmetic operation in microprocessors digital signal processors and data processing application specific integrated circuits In Multiplier Accumulator unit addition and multiplication forms the main blocks High speed and low power MAC units are required for applications of digital signal processing like Fast Fourier Transform Finite Impulse Response filters convolution etc Area and speed of MAC unit are the most significant factors but sometimes increasing speed also increases the power consumption so there is an upper bound of speed for a given power criteria newlineSince the various filter designs found in the Digital Signal Processing applications require computationally efficient multiply and Accumulate operations so the blocks with the desired characteristics have to be chosen carefully The target of this thesis is to design and analysis various adder and multiplication schemes for high speed area efficient and low power operation Multiplier Accumulator unit newline newline