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http://hdl.handle.net/10603/382780
Title: | Design of RNS Based Efficient Arithmetic Circuits |
Researcher: | Patel, Beerendra Kumar |
Guide(s): | Kanungo, Jitendra |
Keywords: | Engineering Engineering and Technology Engineering Electrical and Electronic |
University: | Jaypee University of Engineering and Technology, Guna |
Completed Date: | 2021 |
Abstract: | Digital Signal Processing systems are used for real-time and online-offline processing of pre-loaded data. The Residue Number System (RNS) is a carry-free system used in high-speed arithmetic components like digital signal processing, image processing, and cryptography. The RNS has three categories: (a) Forward Conversion (Binary to Residue Conversion), (b) Moduli channel (Selection of Moduli) (c) Reverse Conversion (Residue to Binary Conversion). The selection of moduli in an RNS-based DSP system significantly impacts the hardware complexity, power consumption, and speed. newlineModulo addition is used to perform the arithmetic operations in the RNS domain. In most RNS-based system designs, the moduli set is preferred. Several techniques to develop the efficient area-delay logic architectures for diminished-1 modulo adders have been proposed in the last decade. The diminished-1 modulo parallel prefix adder structure uses the pre-processing stage , sum computation stage , carry computation stage , and carry increment stage . Modulo multiplier offers higher computational speed than a standard multiplier. It is frequently used in data security and in residue number system design. The modulo multiplier has three basic blocks-partial product generation block, an inverted-end around carry adder tree block, and a diminished-1 modulo adder block. newlineThe main objective of this research work is to reduce the complexity of performing operations. The architecture, based on a parallel prefix tree is helpful for computation at a higher speed. The proposed parallel prefix tree adder improves the speed of multiplication. The reverse converter design consists of residue to binary conversion performed using the Chinese Remainder Theorem (CRT). The design for five moduli sets formulates the wide modular devaluation constrained by using the properties of the Chinese Remainder Theorem (CRT). The proposed works show the efficient designs of RNS based arithmetic circuits newline |
Pagination: | xv;120p. |
URI: | http://hdl.handle.net/10603/382780 |
Appears in Departments: | Department of Electronics and Communication |
Files in This Item:
File | Description | Size | Format | |
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01-title.pdf.pdf | Attached File | 439.07 kB | Adobe PDF | View/Open |
02-certificate.pdf | 552.39 kB | Adobe PDF | View/Open | |
03-abstract.pdf.pdf | 516.31 kB | Adobe PDF | View/Open | |
04-declaration by the scholar.pdf | 435.63 kB | Adobe PDF | View/Open | |
05-acknowledgements.pdf | 454.71 kB | Adobe PDF | View/Open | |
06-contents.pdf.pdf | 851.17 kB | Adobe PDF | View/Open | |
07-list of tables.pdf | 693.25 kB | Adobe PDF | View/Open | |
08-list of figures.pdf | 566.1 kB | Adobe PDF | View/Open | |
09-list of acronyms and abbreviations.pdf | 438.45 kB | Adobe PDF | View/Open | |
10-chapter-1.pdf | 3.65 MB | Adobe PDF | View/Open | |
11-chapter-2.pdf | 2.33 MB | Adobe PDF | View/Open | |
12-chapter-3.pdf | 18.88 MB | Adobe PDF | View/Open | |
13-chapter-4.pdf | 18.19 MB | Adobe PDF | View/Open | |
14-chapter-5.pdf | 12.91 MB | Adobe PDF | View/Open | |
15-chapter-6.pdf | 17.57 MB | Adobe PDF | View/Open | |
16-chapter-7.pdf | 25.14 kB | Adobe PDF | View/Open | |
17-conclusion.pdf | 359.66 kB | Adobe PDF | View/Open | |
18-bibliography.pdf | 89.72 kB | Adobe PDF | View/Open | |
19-list of publications.pdf | 622.63 kB | Adobe PDF | View/Open | |
80_recommendation.pdf | 582.7 kB | Adobe PDF | View/Open |
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