1. Shodhganga@INFLIBNET
  2. Shri Jagdishprasad Jhabarmal Tibarewala University
  3. Faculty of Engineering
Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/382581
Title: A schematic design and implementation of si3n4 hfo2 dual k spacer bulk planar junction less transistor in mixed signal integrated circuits
Researcher: Divya Gampala
Guide(s): Anupama A Deshpande And Baranikunta Harikrishna
Keywords: Engineering
Engineering and Technology
Engineering Electrical and Electronic
University: Shri Jagdishprasad Jhabarmal Tibarewala University
Completed Date: 2021
Abstract: newline
Pagination: 
URI: http://hdl.handle.net/10603/382581
Appears in Departments:Faculty of Engineering

Files in This Item:
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01_title.pdfAttached File101.08 kBAdobe PDFView/Open
02_declaration by the candidate.pdf95.96 kBAdobe PDFView/Open
03_certificate of the supervisor.pdf86.63 kBAdobe PDFView/Open
04_certificate of the co - supervisor.pdf86.77 kBAdobe PDFView/Open
05_acknowledgement.pdf4.98 kBAdobe PDFView/Open
06_table of contents.pdf177.66 kBAdobe PDFView/Open
07_list of tables.pdf8.3 kBAdobe PDFView/Open
08_list of the figures.pdf170.93 kBAdobe PDFView/Open
09_list of graphs.pdf298.1 kBAdobe PDFView/Open
10_abstract.pdf128.39 kBAdobe PDFView/Open
11_chapter01.pdf673.74 kBAdobe PDFView/Open
12_chapter02.pdf384.72 kBAdobe PDFView/Open
13_chapter03.pdf118.41 kBAdobe PDFView/Open
14_chapter04.pdf1.27 MBAdobe PDFView/Open
15_chapter05.pdf498.09 kBAdobe PDFView/Open
16_chapter06.pdf1.48 MBAdobe PDFView/Open
17_chapter07.pdf3.02 MBAdobe PDFView/Open
18_chapter08.pdf144.88 kBAdobe PDFView/Open
19_chapter09.pdf107.49 kBAdobe PDFView/Open
20_references.pdf364.28 kBAdobe PDFView/Open
80_recommendation.pdf250.72 kBAdobe PDFView/Open
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