1. Shodhganga@INFLIBNET
  2. University of Delhi
  3. Dept. of Electronics and Communication Engineering
Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/380122
Title: Design and optimization of digital cmos Integrated circuits for minimum power delay area product
Researcher: Singh, Kunwar
Guide(s): Gupta, Maneesha
Keywords: Digital electronics
Digital integrated circuits
Electronic circuits
Engineering and Technology
Integrated circuits
University: University of Delhi
Completed Date: 2015
Abstract: Available
Pagination: 217 p.
URI: http://hdl.handle.net/10603/380122
Appears in Departments:Dept. of Electronics and Communication Engineering

Files in This Item:
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01_title.pdfAttached File189.87 kBAdobe PDFView/Open
02_certificate.pdf198.3 kBAdobe PDFView/Open
03_declaration.pdf106.22 kBAdobe PDFView/Open
04_acknowledgement.pdf101.39 kBAdobe PDFView/Open
05_abstract.pdf33.17 kBAdobe PDFView/Open
06_table of content.pdf116.88 kBAdobe PDFView/Open
07_list of tables.pdf112.88 kBAdobe PDFView/Open
08_list of figures.pdf117.94 kBAdobe PDFView/Open
09_abbreviation.pdf33.92 kBAdobe PDFView/Open
10_chapter 1.pdf66.49 kBAdobe PDFView/Open
11_chapter 2.pdf830.7 kBAdobe PDFView/Open
12_chapter 3.pdf4.38 MBAdobe PDFView/Open
13_chapter 4.pdf1.57 MBAdobe PDFView/Open
14_chapter 5.pdf309.34 kBAdobe PDFView/Open
15_bibliography.pdf163.77 kBAdobe PDFView/Open
16_appendix.pdf197.63 kBAdobe PDFView/Open
17_list of publications.pdf2.16 MBAdobe PDFView/Open
80_recommendation.pdf552.56 kBAdobe PDFView/Open
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