Advanced Parallel Pipeline Analog To Digital Converter For High Computing Applications

Abstract

The application specific system have a data converter block is one of the core component for computation. The research work carried out to determine ideal and non-ideal parameters of an A/D Converter with different resolution by simulation. Error and jitter block are modelled in Matlab Simulink to analyze the effect of non-ideal aspects and the simulation results are plotted. Mathematical models of dynamic non-ideal characteristics are compared with the resolution of ADC. The simulation results obtained from the modeling of non-ideal parameters are studied and some of the observations are drawn in accordance with ideal characteristics. newlineThe experimental study shows that, as the bandwidth increases resolution also increases in non-ideal characteristics. The 12-bit Pipeline ADC non-idealities are proved through this work. In 12-bit ADC resolution Effective number of bits (ENoB) reaches to zero offset voltage and also ENoB reaches the offset voltage to 0.1V as it decreased to 8-bits. The resolution of a converter decreases as the value of offset voltage increases. newlineIn very large scale integrated (VLSI) design, a challenge is to increase the speed without compromising the power consumption in an analog and mixed mode signal circuit. This research work is carried out to design a 12-bit Pipeline A/D converter (ADC) of 400MS/s sampling rate to meet the high computing requirements. The design is focused to determine high speed and resolution in pipeline ADC to cater different applications. The main advantages of pipeline method are simple to implement, more flexible to improve the speed and makes layout design simple. A proposed technique holds sample and hold circuit (S/H), multiplying DAC, comparator and operational transconductance amplifier (OTA) to design the pipeline ADC architecture. OTA is used to convert differential input voltage into current with the help of a switched capacitor integrator module. newlineA dedicated sample-and-hold amplifier (SHA) is eliminated due to addition of sample-and-hold circuit in the initial stage of Pipeline ADC. Obtained results shows integral and differential non-linear values are +0.61/-0.75LSB and +0.48/-0.55LSB respectively. From simulation the value of Signal to Noise Dynamic Range (SNDR) achieved is 64.2dB and 81.8dB of Spurious Free Dynamic Range (SFDR) is plotted. An EDA platform with cadence tool is used to design, simulate and verified the proposed design on 45nm gpdk library. newline