Certain investigations on low Transition test pattern generator Architecture for built in self test BIST

Abstract

With the advancement in digital VLSI circuit design power newlinedissipation has become a critical concern in recent years driven by the newlineemergence of portable devices in mobile applications Power dissipation is newlineapplicable not only to design power but also for testing power It is because newlinethe large and complex chips require a huge amount of test data and dissipate a newlinesubstantial amount of power during test The reason is that the consecutive newlineinput test vectors are statistically independent which result in increased newlineswitching activity in the circuit during testing There are many test parameters newlinethat should be improved in order to reduce the test cost These parameters newlineinclude the test power test length test application time test fault coverage newlineand test hardware area overhead Hence the research concentrates to develop newlinetechniques which significantly improve the fault coverage with good newlinerandomness test vectors and high correlation between the test vectors newlineacceptable area overhead and minimum test power consumption newlineGLFSR Bipartite Technique BP design is a combination of newlineGLFSR and intermediate patterns insertion technique called Bipartite newlineTechnique BP newline