Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/376189
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DC FieldValueLanguage
dc.coverage.spatial
dc.date.accessioned2022-04-26T08:42:27Z-
dc.date.available2022-04-26T08:42:27Z-
dc.identifier.urihttp://hdl.handle.net/10603/376189-
dc.description.abstractnewline
dc.format.extent144p
dc.languageEnglish
dc.relation
dc.rightsuniversity
dc.titleHigh Performance Binary Logarithmic and BCD Multiplier Architectures
dc.title.alternative
dc.creator.researcherAhmed, Syed Ershad
dc.subject.keywordEngineering
dc.subject.keywordEngineering and Technology
dc.subject.keywordEngineering Electrical and Electronic
dc.description.note
dc.contributor.guideSrinivas, M. B
dc.publisher.placePilani
dc.publisher.universityBirla Institute of Technology and Science
dc.publisher.institutionElectrical and Electronics Engineering
dc.date.registered2009
dc.date.completed2017
dc.date.awarded
dc.format.dimensions
dc.format.accompanyingmaterialDVD
dc.source.universityUniversity
dc.type.degreePh.D.
Appears in Departments:Electrical & Electronics Engineering

Files in This Item:
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01_title.pdfAttached File4.81 MBAdobe PDFView/Open
02_certificate.pdf43.5 kBAdobe PDFView/Open
03_acknowledgement.pdf43.85 kBAdobe PDFView/Open
04_abstract.pdf73.02 kBAdobe PDFView/Open
05_content.pdf77.29 kBAdobe PDFView/Open
06_list of figures, tables and abbreviations.pdf115.35 kBAdobe PDFView/Open
07_chapter 1.pdf95.42 kBAdobe PDFView/Open
08_chapter 2.pdf828.97 kBAdobe PDFView/Open
09_chapter 3.pdf1.07 MBAdobe PDFView/Open
10_chapter 4.pdf712.21 kBAdobe PDFView/Open
11_chapter 5.pdf1.44 MBAdobe PDFView/Open
12_chapter 6.pdf984.07 kBAdobe PDFView/Open
13_chapter 7.pdf72.59 kBAdobe PDFView/Open
14_bibliography.pdf89.11 kBAdobe PDFView/Open
80_recommendation.pdf317.42 kBAdobe PDFView/Open


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