Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/376189
Title: High Performance Binary Logarithmic and BCD Multiplier Architectures
Researcher: Ahmed, Syed Ershad
Guide(s): Srinivas, M. B
Keywords: Engineering
Engineering and Technology
Engineering Electrical and Electronic
University: Birla Institute of Technology and Science
Completed Date: 2017
Abstract: newline
Pagination: 144p
URI: http://hdl.handle.net/10603/376189
Appears in Departments:Electrical & Electronics Engineering

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01_title.pdfAttached File4.81 MBAdobe PDFView/Open
02_certificate.pdf43.5 kBAdobe PDFView/Open
03_acknowledgement.pdf43.85 kBAdobe PDFView/Open
04_abstract.pdf73.02 kBAdobe PDFView/Open
05_content.pdf77.29 kBAdobe PDFView/Open
06_list of figures, tables and abbreviations.pdf115.35 kBAdobe PDFView/Open
07_chapter 1.pdf95.42 kBAdobe PDFView/Open
08_chapter 2.pdf828.97 kBAdobe PDFView/Open
09_chapter 3.pdf1.07 MBAdobe PDFView/Open
10_chapter 4.pdf712.21 kBAdobe PDFView/Open
11_chapter 5.pdf1.44 MBAdobe PDFView/Open
12_chapter 6.pdf984.07 kBAdobe PDFView/Open
13_chapter 7.pdf72.59 kBAdobe PDFView/Open
14_bibliography.pdf89.11 kBAdobe PDFView/Open
80_recommendation.pdf317.42 kBAdobe PDFView/Open
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