Efficient transmitter/receiver architectures for high performance wireless applications

Abstract

Wireless communication has become an integral part of modern society with an ultimate aim of global roaming. The developments in satellite transmission, radio and television broadcasting, and the new generation mobile systems have revolutionized global communication. The recent trend in wireless communication is to implement a single transceiver hardware platform that can support mUltiple communication standards. The progress in CMOS technology opens opportunities to implement flexible platforms at low cost and low power. In this research, analysis has been done on architectures and design techniques that enhances integration and programmability of RF transceivers for wireless communication; and compact, inexpensive, low power communication devices that are robust, testable and capable of handling multiple standards have been developed. The thesis focuses on the development of reconfigurable architectures and high performance building blocks suitable for wireless communication. For efficient multi-mode operation, advanced analog-to-digital converter (ADC) solutions are required with flexibility to adapt to the bandwidth and speed of the high data rate standards. Sigma-delta ADC is the most promising solution to achieve high resolution over a wide variety of bandwidth requirements. The most complex part of a sigma-delta ADC is the digital= decimation filter. So, efficient, high speed and reconfigurable implementation of decimation filter is a key to achieve high performance. The main objectives of the research are to: • Reduce the complexity of decimation filter design by developing a toolbox • Design Residue Number System (RNS) based dual-mode decimation filters for high speed, small die area and low power operation • Reduce the complexity of RNS conversion circuitry • Improve the performance of the communication system through an efficient concatenated coding scheme • Realize easily testable circuits using Reed-Muller (RM) logic The major achievements in this research are the following: • A decimation tilter design toolbox is developed In MALAB® Graphical User Interface Development Environment (GUIDE) which enables the user to perform quick tilter design and analysis for six popular wireless standards. • A reconfigurable RNS based decimation tilter is designed and implemented for WCDMA/WiMAX and WCDMNWLAN dual-mode operation. The performance analysis shows that it has high speed, less area and low power dissipation compared to the implementation in traditional binary number system.