1. Shodhganga@INFLIBNET
  2. University of Mumbai
  3. Electronics and Telecommunication Engineering, Terna Engineering College
Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/375658
Title: Design and Implement FFT Processor With High throughput and Optimum Area with Reduced Complexity
Researcher: Kulkarni, Prasad
Guide(s): Hogade, B.G.
Keywords: Engineering
Engineering and Technology
Engineering Electrical and Electronic
FFT Processor
University: University of Mumbai
Completed Date: 2021
Abstract: newline
Pagination: XIII, 105
URI: http://hdl.handle.net/10603/375658
Appears in Departments:Electronics and Telecommunication Engineering, Terna Engineering College

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01_title.pdfAttached File110.54 kBAdobe PDFView/Open
02_certificate.pdf76.7 kBAdobe PDFView/Open
03_approval sheet.pdf45.82 kBAdobe PDFView/Open
04_statement by the candidate.pdf46.07 kBAdobe PDFView/Open
05_abstract.pdf85.4 kBAdobe PDFView/Open
06_contents.pdf47.99 kBAdobe PDFView/Open
07_list of figures.pdf57.46 kBAdobe PDFView/Open
08_list of tables.pdf56.78 kBAdobe PDFView/Open
09_nomenclature.pdf112.23 kBAdobe PDFView/Open
10_list of acronyms.pdf78.73 kBAdobe PDFView/Open
11_chapter 1.pdf256.64 kBAdobe PDFView/Open
12-chapter 2.pdf153.01 kBAdobe PDFView/Open
13-chapter 3.pdf10.03 MBAdobe PDFView/Open
14_chapter 4.pdf6.29 MBAdobe PDFView/Open
15_chapter 5.pdf5.94 MBAdobe PDFView/Open
16_chapter 6.pdf506.11 kBAdobe PDFView/Open
17_chapter 7.pdf85.9 kBAdobe PDFView/Open
18_bibliography.pdf105.92 kBAdobe PDFView/Open
19-publications.pdf67.07 kBAdobe PDFView/Open
20_copyright & patent.pdf66.25 kBAdobe PDFView/Open
21_similarity index.pdf315.74 kBAdobe PDFView/Open
22_acknowledgement.pdf47.2 kBAdobe PDFView/Open
23_annexures.pdf2.49 MBAdobe PDFView/Open
24-synopsis.pdf9.75 MBAdobe PDFView/Open
80_recommendation.pdf195.93 kBAdobe PDFView/Open
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