Please use this identifier to cite or link to this item:
http://hdl.handle.net/10603/372306
Title: | Efficient domino logic circuits design with Nano FET technologies |
Researcher: | Garg, Sandeep |
Guide(s): | Gupta, Tarun Kumar |
Keywords: | Engineering Engineering and Technology Engineering Electrical and Electronic |
University: | Maulana Azad National Institute of Technology Bhopal |
Completed Date: | 2019 |
Abstract: | newline |
Pagination: | |
URI: | http://hdl.handle.net/10603/372306 |
Appears in Departments: | Department of Electronics and Communication Engineering |
Files in This Item:
File | Description | Size | Format | |
---|---|---|---|---|
01_title.pdf | Attached File | 185.77 kB | Adobe PDF | View/Open |
02_certificate.pdf | 163.21 kB | Adobe PDF | View/Open | |
03_preliminary pages.pdf | 498.88 kB | Adobe PDF | View/Open | |
04_chapter-1.pdf | 643.08 kB | Adobe PDF | View/Open | |
05_chapter-2.pdf | 184.89 kB | Adobe PDF | View/Open | |
06_chapter-3.pdf | 422.82 kB | Adobe PDF | View/Open | |
07_chapter-4.pdf | 651.24 kB | Adobe PDF | View/Open | |
08_chapter-5.pdf | 874.51 kB | Adobe PDF | View/Open | |
09_chapter-6.pdf | 703.38 kB | Adobe PDF | View/Open | |
10_chapter-7.pdf | 331.94 kB | Adobe PDF | View/Open | |
11_bibliography.pdf | 303.36 kB | Adobe PDF | View/Open | |
80_recommendation.pdf | 517.34 kB | Adobe PDF | View/Open |
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