Please use this identifier to cite or link to this item:
http://hdl.handle.net/10603/372300
Title: | Improved VLSI architecture for variable block size motion estimation using SAD in HEVC |
Researcher: | Koshta, Jaya |
Guide(s): | Khare, Kavita |
Keywords: | Engineering Engineering and Technology Engineering Electrical and Electronic |
University: | Maulana Azad National Institute of Technology Bhopal |
Completed Date: | 2019 |
Abstract: | newline |
Pagination: | |
URI: | http://hdl.handle.net/10603/372300 |
Appears in Departments: | Department of Electronics and Communication Engineering |
Files in This Item:
File | Description | Size | Format | |
---|---|---|---|---|
01_title.pdf | Attached File | 98.07 kB | Adobe PDF | View/Open |
02_certificate.pdf | 178.83 kB | Adobe PDF | View/Open | |
03_preliminary pages.pdf | 418.49 kB | Adobe PDF | View/Open | |
04_chapter-1.pdf | 402.55 kB | Adobe PDF | View/Open | |
05_chapter-2.pdf | 336.95 kB | Adobe PDF | View/Open | |
06_chapter-3.pdf | 941.27 kB | Adobe PDF | View/Open | |
07_chapter-4.pdf | 352.72 kB | Adobe PDF | View/Open | |
08_chapter-5.pdf | 978.69 kB | Adobe PDF | View/Open | |
09_chapter-6.pdf | 93.27 kB | Adobe PDF | View/Open | |
10_bibliography.pdf | 223.07 kB | Adobe PDF | View/Open | |
80_recommendation.pdf | 190.31 kB | Adobe PDF | View/Open |
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