Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/372300
Title: Improved VLSI architecture for variable block size motion estimation using SAD in HEVC
Researcher: Koshta, Jaya
Guide(s): Khare, Kavita
Keywords: Engineering
Engineering and Technology
Engineering Electrical and Electronic
University: Maulana Azad National Institute of Technology Bhopal
Completed Date: 2019
Abstract: newline
Pagination: 
URI: http://hdl.handle.net/10603/372300
Appears in Departments:Department of Electronics and Communication Engineering

Files in This Item:
File Description SizeFormat 
01_title.pdfAttached File98.07 kBAdobe PDFView/Open
02_certificate.pdf178.83 kBAdobe PDFView/Open
03_preliminary pages.pdf418.49 kBAdobe PDFView/Open
04_chapter-1.pdf402.55 kBAdobe PDFView/Open
05_chapter-2.pdf336.95 kBAdobe PDFView/Open
06_chapter-3.pdf941.27 kBAdobe PDFView/Open
07_chapter-4.pdf352.72 kBAdobe PDFView/Open
08_chapter-5.pdf978.69 kBAdobe PDFView/Open
09_chapter-6.pdf93.27 kBAdobe PDFView/Open
10_bibliography.pdf223.07 kBAdobe PDFView/Open
80_recommendation.pdf190.31 kBAdobe PDFView/Open
Show full item record


Items in Shodhganga are licensed under Creative Commons Licence Attribution-NonCommercial-ShareAlike 4.0 International (CC BY-NC-SA 4.0).

Altmetric Badge: