Evaluating runtime techniques for leakage power reduction in nano scale cmosvlsi systems

Abstract

In the upcoming days, the electronic devices are expected to be less in size in order to provide the desire portability benefits. Hence it is required that the device must have less weight. The size and the weight of the devices directly affect the power consumption of the electronic devices. Based on these factors the cost of the batteries is determined. Hence, to reduce the cost of the device and enhance the portability feature, the power consumed by the device must be reduced and the reduced size must be attained by decreasing the area of the circuit. Hence, many integrated circuit technologies have been developed since. Very Large Scale Integration (VLSI) technology contains a lot of electronic circuits on a single silicon chip. This technology is widely employed in many fields like Communication networks, Digital Signal Processing, Computers, Medical equipment s, etc. These goals can be achieved with the help of applying faster clocking circuits and the faster performing devices can be obtained. The technological improvement in integrated circuits enables to obtain small size circuits using Deep Submicron (DSM) technology. Hence even a very large circuit to accomplish complex functions can be designed as a small size device. However, the number of transistors occupied in a chip increases, which increases the power dissipation of the chip. The modern portable devices like mobile phones, laptops, Personal Digital Assistants (PDAs) operate from battery power. The lifetime of a battery of these devices is affected by large power dissipation. This also affects the performance of the devices. Therefore, to increase the performance, more expensive cooling system is required. The dynamic power dissipation is occurring due to the charging and discharging of load capacitances and it varies depending on the supply voltage level. Hence, many researchers have taken attempts to lessen the supply voltage to get less dynamic power dissipation. Moreover the threshold voltage must be decreased to increase the switching speed of the transistor. But the shortcoming is the leakage power dissipation due to the threshold voltage reducti In case of miniaturized electronics, it possesses leakage current in the active and standby mode since sub threshold leakage leads to the high power intemperance. However, there are numerous works have been considered in order to accomplish low power consumption in CMOS VLSI circuits. In our work, a Vbody control system related to the concept of Sleepy Lector design which decrease standby leakage power of CMOS. Vbody control system produces a finest reverse body-bias voltage on or after leakage monitoring circuit. In the first work the NAND gate and NOR gate are designed with the Sleepy Keeper and its performance is compared with the implementation using other approaches. Then the reverse body biasing technique is adopted and a Sleepy Lector concept is applied to it. In addition, some clocking circuits such as Clock Gating, Energy Recovery Clock, Clock Enable and Clock Boosting are also applied to increase the speed of the circuit and the following circuits are obtained; Clock Enable Sleepy Lector (CESL), Clock Gating Sleepy Lector (CGSL), Clock Boosting Sleepy Lector(CBSL) and Energy Recovery Clock Sleepy Lector (ERCSL). However, the consequences of these implementations are equated in order to investigate intended for the performance that to be better. Sleepy Lector also decreases leakage current through familiarizing sleep transistors and Leakage Controlled Transistor (LCT). In case of Energy recovery circuit, it regulates the flow of current by the way of fixing low voltage drop through the device. Thus, the Clock gating bargains decrease of clock power. The proposed optimal Vbody control systems are applied and replicated in HSPICE by means of 32nm N-MOSFET equipment. The consequences are assessed by ISCAS85 benchmark circuits designed for two dissimilar operating temperatures such as 25oC and 100oC. Therefore, the maximum reduction in leakage of power consumption of the proposed methods CESL, CGSL, CBS newline