Analysis of Clock Gating Conditional Pulse Enhancement And Signal Feed Through In Pulse Triggered Flip Flops

Abstract

A major contributor to the total power in the present-day advanced digital system is the clock distribution network, which can disperse an extensive of the total power for high-performance applications. Moreover, the expanded complexity and the demanding performance in high-speed Very Large Scale Integration (VLSI) systems increment the clock load, which aggravates the clock power dissipation. This viewpoint convinces the researchers and designers to discover a novel low-power and high-speed solutions for the clock distribution, to encourage the rise in chip usefulness. Flip-Flops (FFs) are the essential storage components utilized widely in a wide range of digital designs. Specifically, computerized plans in these days regularly receive concentrated pipelining procedures and utilize numerous FF-rich modules. It is additionally assessed that the power utilization of the clock system, which comprises of clock distribution systems and storage elements, is as high as 20%-40% of the total system power. newlinePulse-triggered FF (P-FF) has been viewed as a famous option in contrast to the conventional master-slave-based FF in the utilization of high-speed operations. Other than the speed advantage, its circuit simplicity is additionally useful for bringing down the power utilization of the clock tree network. Depending upon the method of pulse generation, P-FF designs can be named as implicit or explicit. In an Implicit P-FF, the pulse generator is in-built in the latch design, and no explicit pulse signals are produced. Implicit P-FFs have more speed and power-efficient than explicit if a single latch is utilized. On the other hand, conventional P-FFs faces pulse width control issue, longest discharge path issues, and undesirable switching activities at sleep/idle mode of operation. newlineIn this research, three implicit P-FFs are proposed for low power and high-speed applications. The clock gating concept, conditional pulse enhancement scheme and signal feed-through mechanism are the strategies proposed in this researc