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http://hdl.handle.net/10603/366527
Title: | An Implicit Analysis of Impact OF Resistive Open Faults on Low Power Nanometric Static Rams |
Researcher: | Gangaiah Yadav C. |
Guide(s): | K.S. Vijula Grace |
Keywords: | Engineering Engineering and Technology Engineering Electrical and Electronic |
University: | Noorul Islam Centre for Higher Education |
Completed Date: | 2021 |
Abstract: | The present whole world depended out and out on digital technology. From taking food of the humans to their health condition are monitored by using appropriate digital devices. Of them, mobile phone became as a daily usage thing for every human. In these digital devices for storing of past data for future reference purpose need memory unit. Now-a-days, every house also comprises a few digital electronic devices. The Random Access Memories (RAMs)play a pivotal role in digital world. The RAMs are two types, they are Static and Dynamic. The accessing speed of Dynamic memory is slower than that Static Random Access Memory(SRAM) but rather cost effective. The SRAM play a powerful role in digital world. Many of the digital electronic devices are fabricated with SRAM cells. newline newlineDesign of low power SRAMs is a complex task now-a-days. The reducing size of the transistor is a major design challenge for fabricating of low power and high speed SRAMs. The reducing in size shows an immense impact on the power and delay parameters. For scaling of circuits at present are available different advanced technologies. During the fabrication these low power SRAMs generate different kinds of faults. One of the significant faults is Resistive Open Fault (ROF). newline newlineRecent Integrated Circuit (IC) based design technological devices are regrettably damaged by several undesired side effects. One of undesired side effects is ROF. Increase in level of leakage current and decrease in conductivity of circuit are the major reasons of these undesired side effects. The severe affect caused by more leakage current is functionality declining of the SRAM cells, which can be modelled with a data retention fault where the memory celllost its stored value. Another serious effect caused by decreasing in conductivity is a delay fault.In the present research proposal the designed low power nanometric SRAMs are with 6 Transistors, 7 Transistors, 8 Transistors and 9 Transistors in three different nanometric technologies, i.e. 180 nm , 90 nm and 45 nm . Moreover, th |
Pagination: | 5529 Kb |
URI: | http://hdl.handle.net/10603/366527 |
Appears in Departments: | Department of Electronics and Communication Engineering |
Files in This Item:
File | Description | Size | Format | |
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80_recommendation.pdf | Attached File | 335.92 kB | Adobe PDF | View/Open |
certificate.pdf | 516.87 kB | Adobe PDF | View/Open | |
chapter 1.pdf | 259.9 kB | Adobe PDF | View/Open | |
chapter 2.pdf | 426.91 kB | Adobe PDF | View/Open | |
chapter 3.pdf | 3.35 MB | Adobe PDF | View/Open | |
chapter 4.pdf | 2.28 MB | Adobe PDF | View/Open | |
chapter 5.pdf | 4.32 MB | Adobe PDF | View/Open | |
chapter 6.pdf | 1.93 MB | Adobe PDF | View/Open | |
chapter 7.pdf | 41.63 kB | Adobe PDF | View/Open | |
front page.pdf | 266.71 kB | Adobe PDF | View/Open | |
list of publications based on thesis.pdf | 44.83 kB | Adobe PDF | View/Open | |
references.pdf | 101.55 kB | Adobe PDF | View/Open | |
table of contents.pdf | 284.98 kB | Adobe PDF | View/Open |
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