Performance Efficiency Determination Of Fir Filter Techniques In Channelization Of Software Defined Radio

Abstract

With the growing demand for high-speed data, video streaming, spectral newlineefficiency and lower latency the software-defined radio (SDR) technology newlinebecome a vital part of the 5G wireless communication technology. SDR is newlinemainly used to provide the addition of new features or capabilities to an newlineinfrastructure currently in use by reconfiguring the single hardware platform. newlineSDR supports the existing and future wireless protocol standards by changing newlinethe software routine without the alteration of hardware. newlineThe abstraction of a distinct radio channel from the numerous wireless protocol newlinestandards in SDR is implemented by the digital finite impulse response (FIR) newlinefilter. This research work focuses on performance analysis of various FIR filter newlinearchitectures to achieve multi-standard channelization and extraction of desired newlinefrequency band. One of the major techniques for the calculation of inner product newlineis distributed arithmetic (DA) based FIR filter which uses a lookup table (LUT) newlineto eliminate the need for the multiplier. The efficiency of the DA filter is newlineaffected by the increasing number of address line and also due to its serial newlineoperation. To overcome this problem parallel and pipeline based DA filter using newlineoffset binary coding (OBC) for two-bit at a time (2-BAAT) is proposed in our newlineresearch work for stationary and reconfigurable application. The proposed work newlineachieves less area and delay than the existing method. newlineIn the second stage of our research work, an efficient high-speed 32-bit carry newlineselect adder (CSLA) is proposed for the design of the FIR filter. In the proposed newlinemethod the carry propagation time is reduced with the buffer in the CSLA newlinearchitecture. This proposed method offers a 37% reduction in delay when newlinecompared with the existing CSLA. newlineThe sample rate conversion (SRC) is one of the core blocks in SDR receiver to newlineconsiderably reduce the data rate for the efficient processing of the data in a newlinefield-programmable gate array (FPGA).