Design and implementation of new hardware architecture for image splitting and enlargement using fpga

Abstract

In recent past it has been noticed that there is a necessity of displaying a high quality image on a big screen display. To achieve this big display we need a big screen with a very high cost. Alternate solution is instead of displaying image on one big screen, it is preferred to have a use of multiple screens to make a combined one screen. The above mentioned solution requires a software controlled system to perform the operation. The software controlled system has got certain limitation such as, expert team should require for the complete operation of software system. It requires a complete system with additional hardware. It may also affect the quality of image due to slow in the system RAM and processor speed. It also leads to limitation like power, cost, operating speed, man power and hardware. This research is focused on design and development of new hardware architecture for image splitting and enlargement using FPGA. In this research work FPGA based system is designed, which is used eliminates the above said problems. In order to achieve the above said problems, we have implemented a counter specific splitting algorithm for image splitting and bilinear interpolation technique is used to enlarge the quality of the image. The designed architecture is verified using the matlab simulink for its operational output. The same architecture is further developed on system generator to obtain the hardware results. The optimization of the results for the reduced hardware has been developed on FPGA platform using Artix-7 FPGA. The overall FPGA design process is divided in to three parts: The image splitting block, image interpolation block, and image generation top module. Synthesis for image splitting, image interpolation and image generation top module is carried out using the Xilinx ISE 14.7 and simulated using the modelsim 6.3C. Once the simulation results are obtained, functionality of all three top modules is verified with waveforms.