Improved switching performance of gate all around mosfet for next generation cmos devices

Abstract

newline The demand of the next generation computing system at the sub nano scale regime is to newlinedevelop some state of the art CMOS inverters. Those systems will deliver high newlineperformance, robust to noise and will be energy efficient. Miniaturization in the size of newlineCMOS inverters has allow them to improve the packing density and hence performance. newlineHowever, the basic parameters like noise margin, switching current and transient response newlineshould be improved to bring the device into the frame of next generation expectations. Use newlineof multi metal gate engineering to the transistor enhances the carrier mobility thereby newlinereducing the short channel effects. Conversely, use of these transistors for next generation newlineCMOS devices is blocking the path when it explains the VTC and delay calculations. newlineTherefore, some other gate engineering technique must be there to mitigate the current newlineproblems associated with multi metal gate engineering technique. newlineIn this thesis, a new work-function modulated CMOS inverter is proposed. In the proposed newlinework, instead of using control gate and screening gate of different work-function, the newlinecontrol gate is modulated by introducing a binary alloy whose work-function varies linearly newlinewith mole fraction variation. This thesis describes a state of the art CMOS inverter with newlinelow power, low transition delay, high noise margin and improved switching current. The newlinefigure of merits of the proposed CMOS inverter are compared with the multi metal gate newlineengineered CMOS inverter parameters. The comparison is carried out with individual newlinetransistor characteristic analysis for nMOS and pMOS also. The simulatio