Please use this identifier to cite or link to this item:
http://hdl.handle.net/10603/363017
Title: | An Augmented Approach on Design of Multipliers for Linear Phase FIR Filter using FPGA and its Implementation |
Researcher: | M Sakthimohan |
Guide(s): | J Deny |
Keywords: | Engineering Engineering and Technology Engineering Electrical and Electronic |
University: | Kalasalingam University |
Completed Date: | 2021 |
Abstract: | newline |
Pagination: | |
URI: | http://hdl.handle.net/10603/363017 |
Appears in Departments: | Department of Electronics and Communication Engineering |
Files in This Item:
File | Description | Size | Format | |
---|---|---|---|---|
201808265 sakthimohan thesis.pdf | Attached File | 9.38 MB | Adobe PDF | View/Open |
80_recommendation.pdf | 186.62 kB | Adobe PDF | View/Open |
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