An Augmented Approach on Design of Multipliers for Linear Phase FIR Filter using FPGA and its Implementation

Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/363017

Full metadata record

DC Field	Value	Language
dc.coverage.spatial
dc.date.accessioned	2022-02-16T10:20:29Z	-
dc.date.available	2022-02-16T10:20:29Z	-
dc.identifier.uri	http://hdl.handle.net/10603/363017	-
dc.description.abstract	newline
dc.format.extent
dc.language	English
dc.relation
dc.rights	university
dc.title	An Augmented Approach on Design of Multipliers for Linear Phase FIR Filter using FPGA and its Implementation
dc.title.alternative
dc.creator.researcher	M Sakthimohan
dc.subject.keyword	Engineering
dc.subject.keyword	Engineering and Technology
dc.subject.keyword	Engineering Electrical and Electronic
dc.description.note
dc.contributor.guide	J Deny
dc.publisher.place	Virudhunagar
dc.publisher.university	Kalasalingam University
dc.publisher.institution	Department of Electronics and Communication Engineering
dc.date.registered	2018
dc.date.completed	2021
dc.date.awarded	2022
dc.format.dimensions
dc.format.accompanyingmaterial	DVD
dc.source.university	University
dc.type.degree	Ph.D.
Appears in Departments:	Department of Electronics and Communication Engineering

Files in This Item:

File	Description	Size	Format
201808265 sakthimohan thesis.pdf	Attached File	9.38 MB	Adobe PDF	View/Open
80_recommendation.pdf		186.62 kB	Adobe PDF	View/Open

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