Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/358355
Title: Development of Test Power and Test Data Volume Reduction Methods in Digital VLSI Circuits
Researcher: Mitra, Sanjoy
Guide(s): Das, Debaprasad
Keywords: Computer Science
Computer Science Software Engineering
Engineering and Technology
University: Assam University
Completed Date: 2019
Abstract: newline
Pagination: vi, 124p.
URI: http://hdl.handle.net/10603/358355
Appears in Departments:Department of Computer Science and Engineering

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01_title page.pdfAttached File66.52 kBAdobe PDFView/Open
02_certificate.pdf58.15 kBAdobe PDFView/Open
03_preliminary pages.pdf954.08 kBAdobe PDFView/Open
04_abstract.pdf241.55 kBAdobe PDFView/Open
05_chapter 1.pdf2.09 MBAdobe PDFView/Open
06_chapter 2.pdf5.26 MBAdobe PDFView/Open
07_chapter 3.pdf5.84 MBAdobe PDFView/Open
08_chapter 4.pdf2.17 MBAdobe PDFView/Open
09_chapter 5.pdf3.75 MBAdobe PDFView/Open
10_chapter 6.pdf219.05 kBAdobe PDFView/Open
11_bibliography.pdf3.48 MBAdobe PDFView/Open
12_annexure i.pdf552.71 kBAdobe PDFView/Open
13_annexure ii.pdf711.61 kBAdobe PDFView/Open
14_annexure iii.pdf2.52 MBAdobe PDFView/Open
80_recommendation.pdf284.81 kBAdobe PDFView/Open
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