Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/357667
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dc.coverage.spatial
dc.date.accessioned2022-01-24T09:53:12Z-
dc.date.available2022-01-24T09:53:12Z-
dc.identifier.urihttp://hdl.handle.net/10603/357667-
dc.description.abstractAttached newline
dc.format.extentx, 155
dc.languageEnglish
dc.relation
dc.rightsuniversity
dc.titleReliability Aware Analysis and Design of Network on Chip
dc.title.alternative
dc.creator.researcherSHARMA, ASHISH
dc.subject.keywordComputer Science
dc.subject.keywordComputer Science Hardware and Architecture
dc.subject.keywordEngineering and Technology
dc.description.note
dc.contributor.guideGaur, Manoj Singh and Bhargava, Lava
dc.publisher.placeJaipur
dc.publisher.universityMalaviya National Institute of Technology Jaipur
dc.publisher.institutionDepartment of Computer Science and Engineering
dc.date.registered2013
dc.date.completed2019
dc.date.awarded2019
dc.format.dimensions
dc.format.accompanyingmaterialDVD
dc.source.universityUniversity
dc.type.degreePh.D.
Appears in Departments:Department of Computer Science and Engineering

Files in This Item:
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01_title.pdfAttached File168.61 kBAdobe PDFView/Open
02_certtficate.pdf63.04 kBAdobe PDFView/Open
03_abstract.pdf86.61 kBAdobe PDFView/Open
04_declaration.pdf55.19 kBAdobe PDFView/Open
05_acknowledgement.pdf49.45 kBAdobe PDFView/Open
06_contents.pdf90.58 kBAdobe PDFView/Open
07_list_of_tables.pdf45.17 kBAdobe PDFView/Open
08 list_of_figures.pdf148.94 kBAdobe PDFView/Open
10_chapter2.pdf1.81 MBAdobe PDFView/Open
11_chapter3.pdf2.17 MBAdobe PDFView/Open
12_chapter4.pdf3.11 MBAdobe PDFView/Open
13_chapter5.pdf397.15 kBAdobe PDFView/Open
14_chapter6.pdf957.33 kBAdobe PDFView/Open
15_bibliography.pdf161.36 kBAdobe PDFView/Open
16_appendix.pdf3.57 MBAdobe PDFView/Open
80_recommendation.pdf303.09 kBAdobe PDFView/Open
9_chapter1.pdf609.3 kBAdobe PDFView/Open


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