1. Shodhganga@INFLIBNET
  2. Malaviya National Institute of Technology Jaipur
  3. Department of Computer Science and Engineering
Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/357667
Title: Reliability Aware Analysis and Design of Network on Chip
Researcher: SHARMA, ASHISH
Guide(s): Gaur, Manoj Singh and Bhargava, Lava
Keywords: Computer Science
Computer Science Hardware and Architecture
Engineering and Technology
University: Malaviya National Institute of Technology Jaipur
Completed Date: 2019
Abstract: Attached newline
Pagination: x, 155
URI: http://hdl.handle.net/10603/357667
Appears in Departments:Department of Computer Science and Engineering

Files in This Item:
File Description SizeFormat 
01_title.pdfAttached File168.61 kBAdobe PDFView/Open
02_certtficate.pdf63.04 kBAdobe PDFView/Open
03_abstract.pdf86.61 kBAdobe PDFView/Open
04_declaration.pdf55.19 kBAdobe PDFView/Open
05_acknowledgement.pdf49.45 kBAdobe PDFView/Open
06_contents.pdf90.58 kBAdobe PDFView/Open
07_list_of_tables.pdf45.17 kBAdobe PDFView/Open
08 list_of_figures.pdf148.94 kBAdobe PDFView/Open
10_chapter2.pdf1.81 MBAdobe PDFView/Open
11_chapter3.pdf2.17 MBAdobe PDFView/Open
12_chapter4.pdf3.11 MBAdobe PDFView/Open
13_chapter5.pdf397.15 kBAdobe PDFView/Open
14_chapter6.pdf957.33 kBAdobe PDFView/Open
15_bibliography.pdf161.36 kBAdobe PDFView/Open
16_appendix.pdf3.57 MBAdobe PDFView/Open
80_recommendation.pdf303.09 kBAdobe PDFView/Open
9_chapter1.pdf609.3 kBAdobe PDFView/Open
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