Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/357244
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DC FieldValueLanguage
dc.coverage.spatialElectronics and Communication engineering-
dc.date.accessioned2022-01-20T11:43:38Z-
dc.date.available2022-01-20T11:43:38Z-
dc.identifier.urihttp://hdl.handle.net/10603/357244-
dc.description.abstractfile attached-
dc.format.extent70 p.-
dc.languageEnglish-
dc.relationno. of references 42-
dc.rightsuniversity-
dc.titleResource efficient FPGA implementation and weighted logarithmic model for enhancement of fog degraded images-
dc.title.alternative--
dc.creator.researcherGupta, Hitendra-
dc.subject.keywordEngineering and Technology-
dc.subject.keywordEngineering-
dc.subject.keywordEngineering Electrical and Electronic-
dc.subject.keywordField programmable gate arrays-
dc.subject.keywordProgrammable logic devices-
dc.subject.keywordLogarithmic functions-
dc.subject.keywordLogarithms-
dc.description.notereferences given-
dc.contributor.guideSharma, K K-
dc.publisher.placeJaipur-
dc.publisher.universityMalaviya National Institute of Technology Jaipur-
dc.publisher.institutionDepartment of electronics and communication engineering-
dc.date.completed2019-
dc.format.dimensions--
dc.format.accompanyingmaterialNone-
dc.type.degreePh.D.-
dc.source.inflibnetINFLIBNET-
Appears in Departments:Department of Electronics and Communication Engineering

Files in This Item:
File Description SizeFormat 
01_title.pdfAttached File348.46 kBAdobe PDFView/Open
02_declaration.pdf120.1 kBAdobe PDFView/Open
03_certificate.pdf99.15 kBAdobe PDFView/Open
04_acknowledgement.pdf91 kBAdobe PDFView/Open
05_abstract.pdf97.34 kBAdobe PDFView/Open
06_content.pdf211.82 kBAdobe PDFView/Open
07_chapter 1.pdf110.2 kBAdobe PDFView/Open
08_chapter 2.pdf733.88 kBAdobe PDFView/Open
09_chapter 3.pdf1.1 MBAdobe PDFView/Open
10_chapter 4.pdf1.77 MBAdobe PDFView/Open
11_references.pdf163.4 kBAdobe PDFView/Open
80_recommendation.pdf358.17 kBAdobe PDFView/Open


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