Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/356557
Title: Design and Implementation of Energy Efficient Memory and Logic Circuits Exploring Post CMOS Devices at Low VDD
Researcher: SUDHA VANI YAMANI
Guide(s): USHA RANI NELAKUDITI, RAMESH VADDI
Keywords: Engineering and Technology
Engineering
Instruments and Instrumentation
University: Vignans Foundation for Science Technology and Research
Completed Date: 2021
Abstract: Embedded memories play an important role and occupy large area in modern System- on-Chips (SoCs) and emerging In-memory computing applications targeting AI applications. CMOS based SRAM designs with 6T cell has several limitations such as read instability, degradation of Read Static Noise Margin (RSNM), reduction in write ability and poor read performance with scaling in supply voltage (VDD). To enhance the read stability/ability and write ability of 6T SRAM cell designs at scaled voltages, it requires good read/write assist circuits and robust sense amplifier circuits. First part of this work as Chapter 3 concentrate on enhancing the read stability/ability of 6T SRAM cell designs at scaled supply voltages of 0.5V. In this, I have proposed a diode-based and double diode-based Word Line Under Drive Read Assist (WLUD-RA) circuits to enhance the read stability and RSNM. In the next part of this work, I have concentrated on enhancing the read performance of the 6T SRAM cell by a novel sense amplifier circuit design to offset compensation and enhance the read performance. The proposed circuits are designed in 90nm CMOS technology in a Cadence spectre environment and they are simulated and analysed with various process corners and temperatures along with Monte Carlo (MC) analysis to a sense amplifier. At the simulation process, the proposed double diode-based WLUD scheme offers RSNM improvement of 45.8% at Slow NMOS Fast PMOS (SNFP) corner and 26.3% at Fast NMOS Slow PMOS (FNSP) corner, compared with existing WLUD and also the proposed novel sense amplifier achieves a 4X offset improvement with an area overhead of 1.1% and a power overhead of 2.9%. newlineRecently, emerging Non-volatile memory technologies such as Phase Change Random- newlineAccess Memory (PCRAM), Resistive RAM (ReRAM), Ferroelectric RAM (FeRAM), and Spin Transfer Torque Magnetic RAM (STT-MRAM) etc, have gained significant research attention along with the conventional designs.
Pagination: 174
URI: http://hdl.handle.net/10603/356557
Appears in Departments:Department of Electronics and Communication Engineering

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6_chapter-3.pdf1.27 MBAdobe PDFView/Open
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9_chapter-6.pdf2.49 MBAdobe PDFView/Open
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