Investigations On Delay and Power Minimization Techniques in 90nm On Chip Interconnects

Abstract

The ever increasing circuit complexity led by Moore s law with the newlinecontinuous scaling of CMOS technology has made the role of interconnects in newlinethe submicron technology nodes very prominent. However conventional copper newlinewires face tremendous challenges of the nanometer technology where the newlinerequirement is of reliable high speed wires with minimal crosstalk effects. newlineMoreover, the circuits now can be clocked at ever increasing signal edge rates newlineand frequencies. On the contrary, as lateral dimensions are scaled aggressively newlinecompared to vertical dimensions, the coupling capacitance among adjacent newlineinterconnects has a huge impact on the overall IC performance .There is a need newlineof study of coupling capacitance and inductance effect among adjacent newlineinterconnects in IC technology. But there is a limitation of coupling capacitance in newlinemultilayer structure. However, the mutual inductance is not limited to adjacent newlinewires and layers and it exists among all parallel wires. The capacitive and newlineinductive effects lead to crosstalk induced delay, noise and associated power newlinedissipation which affects the signal integrity and degrades the performance of the newlinecircuit. The feature set of VLSI devices has been reduced drastically with newlineincreasing number of years. The billion numbers of transistors are newlineaccommodated in a single IC. Due to the device geometries are shrinking in such newlinea way that the dependence on the interconnect delay. However the interconnect newlinedelay becomes more significant in IC. At the same time designing, modeling and newlineoptimization of interconnects which becomes difficult. This research work focus newlineon effects of cross talk in interconnects delay in VLSI device. The model of VLSI newlinecircuit has been developed and optimization technique has been used to newlinecompute and evaluate the performance of distributed RLC interconnects. The newlinemain objective of this research work to minimize the delay and power in deep newlinesubmicron VLSI interconnects. This has been achieved by introducing a novel newlinevoltage doubling technique.