Design and Simulation of Silicon Nanowire Transistors at the Scaling Limit

Abstract

newlineOver the last decades, driven by the continuous demand for high performance, MOSFET newlinedevices have undergone a shrinkage in the size at an exponential rate. Although this newlinedownscaling has enhanced the device performance, it has brought a host of issues that newlinehave become extremely relevant with every generation of the technological node. Apart newlinefrom the short channel effects (SCE), variability in transistor characteristics is one of the newlineprimary roadblocks to device scaling. Despite considerable efforts to control process newlinevariations, there exist intrinsic sources of dispersion in devices, which arise due to the newlineprocess variations. The main process variation sources are the Random Discrete Dopants newline(RDD) and Metal Gate Granularity (MGG). Impacts of the number and spatial distribution newlineof random discrete dopants and metal gate granularity on the variability of transistor newlinecharacteristics (mainly, subthreshold slope, DIBL, threshold voltage, OFF- and ONcurrents) newlinehave been studied in detail. newlineStudies using computer aided simulations provide an excellent way in understanding and newlineevaluating the impact of these variation sources on the device performance. In this thesis, newlineseveral available TCAD tools have been used for the design and simulation of silicon newlinenanowire Field Effect Transistors (NWFETs). The geometry parameters like diameter and newlinelength of the channel, substrate orientation were varied and the performance of NWFETs newlineare reported. Improved performance has been obtained by implementing stressors newline(mobility boosters) in the source-drain extension and channel region. By increasing the newlinenumber of nanowires, improved performance has also been obtained. Stress techniques newlinehave been used to enhance device performance. SiGe stressor has been introduced in the newlinesource/drain and channel regions. The effects of stressor design by changing the channel newlinematerial has been presented. newlineTo have a more realistic understanding of the variability of threshold voltage (VT) due to newlinethe spatial distribution of metal grains and random discrete dopants, 3D simulations were newlineperformed by considering the dopants in a 3D structure to study the influence of dopant newlinedistribution not just along the channel length but also along the channel width. The newlinedependence of the VT variability on the device dimensions due to dopants was also newlineinvestigated. The location and number of the dopants were varied both along the length (xviii newlinedirection) and along the width (z-direction). The results showed the threshold voltage is newlineinfluenced by the location of the dopants along the channel length. When dopants sites newlinewere aligned along the length then, the resulting overall VT is mostly contributed by newlinedopants that were located close to the channel center. These behaviors were interpreted by newlineconsidering the effective barrier area created by the dopants, which depends on the newlineseparation between them and their locations along the channel length and width. Finally, newlinewe studied the simultaneous influence of random discrete dopants and metal gate newlinegranularity on the device performance. newlineThe degradation characteristics are also studied. The reliability issues in silicon nanowire newlinetransistors have been addressed by using the H/H2 reaction-diffusion (RD) model for newlineinterface traps generation and recovery during and after stressing. Gate-all-around Si newlinenanowire transistors show a fast initial degradation, quick degradation saturation, and newlinerecovery behavior. To conclude, the work done in this thesis has shown that the number newlineand spatial distribution of random discrete dopants and metal gate granularity are newlinesignificant contributors to the variability in device performance in ultra-scaled nanowire newlinetransistors. Using physics-based 3D TCAD simulations and device optimization at 5nm newlinetechnology node, we are able to show possible improvements in critical design parameters newlinefor the vertically stacked NWFETs to surpass current FinFET technology.