Coding Techniques for Reliable Packet Transmission through Low Power Network on Chip Interconnects

Abstract

In Ultra Deep Sub Micron (UDSM) technology, the crucial issues in the NoC design are to meet the performance, power consumption requirements of the SoC and to simultaneously address reliability, interconnect delay, and crosstalk noise. Therefore, it is vital to choose an optimal coding technique to improve communication reliability and reduce self and coupling switching activities. There is no coding technique that addresses reliability and self and coupling switching activities in an optimized way. Thus, the need for a technique that handles and reduces all the effects that arise due to crosstalk and reliability has been identified as a research gap. Therefore, the main focus of this work is to design and develop a coding technique for its implementation at the data link layer of NoC to address reliability, power consumption, and self and coupling switching activities. The technique is analyzed and evaluated for the attainable level of reliability and the reduction in switching activities. Reliability is mainly evaluated based on the probability of residual transient errors. By incorporating the coding technique in the NoC router, the required link swing voltage, link power consumption, and link energy consumption are calculated. The percentage of switching activity reduction is derived by evaluating the percentage of power savings that are achievable in the NoC link. Further, the proposed and existing techniques are implemented at 45 nm technology to assess the area occupancy, power consumption, and delay of codec and the NoC router. The technique s performance is also evaluated by calculating the average latency taken by the packets during their travel from the source processing element to the destination processing element in NoC coding technique. newline