Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/354560
Title: Enhanced Hardware Trojan Detection and Prevention Techniques to Ensure a Secured Hardware With Improved Performance Metrics
Researcher: Sree Ranjani R
Guide(s): Nirmala Devi M
Keywords: Engineering and Technology; Engineering Electrical and Electronic; Electronics and Communication Engineering; Hardware Trojan ; Fault Analysis; integrated circuit; cryptographic; VLSI; Very-Large-Scale Integration; encryption;decryption circuit theory; Hardware Encryption; Attack; Brute force attack
University: Amrita Vishwa Vidyapeetham University
Completed Date: 2019
Abstract: Globalization of the integrated circuit (IC) design flow leads to many hardware vulnerabilities. Outsourcing various steps is common in the fabless IC manufacturing industry. These fabless industries have to depend on the untrustworthy fabrication units where the attacker has easy access to the implementation of the IC at any stage of the original design. Some untrusted fabrication companies may illegally overbuild ICs and sell them in the market or the attacker in the fabrication unit may add a malicious circuit called Hardware Trojan (HT) to the original design. These hardware related security issues directly affect the efficiency of the architectures, specifically in military, finance and cryptographic applications. Hence a secured hardware is necessary to upgrade the performance, reliability and efficiency of any mission critical system. Hardware security includes both detection and prevention of malware in modern IC design and manufacturing practices. HT detection, diagnosis and design-for-trust techniques regain the trust of end-users. The existing detection techniques refine the hard decision due to design complexity and in case of prevention technique high design overhead have been reported. These techniques have varying degrees of complexity and performance enhancement and hence require an enhanced technique to build a secured hardware during all the three phases of design, viz., design phase, test phase, and execution phase. An attempt is made in this thesis to achieve the above goal. To enhance HT detection during the test time, a scalable HT detection and diagnosis without referring to golden-chip is proposed. It is executed by selecting important nodes to measure the dynamic leakage power for a specific set of input patterns. This scheme provides a reduced time complexity with minimal power measurements due to segmentation and re-use of the measurements. Thus an enhanced detection technique during the test-phase, with the improved detection accuracy and to obviate false positives Trojan detection...
Pagination: xi, 122
URI: http://hdl.handle.net/10603/354560
Appears in Departments:Department of Electronics & Communication Engineering (Amrita School of Engineering)

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02_certificate.pdf208.38 kBAdobe PDFView/Open
03_declaration.pdf174.33 kBAdobe PDFView/Open
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06_acknowledgement.pdf289.35 kBAdobe PDFView/Open
07_list of figure.pdf292.88 kBAdobe PDFView/Open
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09_abbreviation.pdf296.61 kBAdobe PDFView/Open
10_list of symbols.pdf490.33 kBAdobe PDFView/Open
11_abstract.pdf293.04 kBAdobe PDFView/Open
12_chapter 1.pdf321.52 kBAdobe PDFView/Open
13_chapter 2.pdf389.36 kBAdobe PDFView/Open
14_chapter 3.pdf435.91 kBAdobe PDFView/Open
15_chapter 4.pdf1.21 MBAdobe PDFView/Open
16_chapter 5.pdf1.05 MBAdobe PDFView/Open
17_chapter 6.pdf994.74 kBAdobe PDFView/Open
18_chapter 7.pdf254.27 kBAdobe PDFView/Open
19_references.pdf186.04 kBAdobe PDFView/Open
80_recommendation.pdf291.68 kBAdobe PDFView/Open
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