Developing Fpga Architecture Of All Digital Phase Locked Loop With Power Reduction And Improved Frequency Resolution For Wireless Application

Abstract

Internet of things (IoT) improves performance on wireless sensor-based communications and built-in human applications. All Digital Phase Locked Loop (ADPLL) consists of three modules namely phase detector, loop filter and forbidden oscillator, digital in nature. ADPLL is used to generate Radio Frequency local oscillator signals for converting baseband signal to Radio Frequencysignal in IoT applications. Therefore, the local oscillator signal value from ADPLL should be with high frequency resolution, low interruption time, and low power consumption. newline newline newlineWe have designed an ADPLL with enhanced sampling technique (ES-DPLL), modified bang algorithm and a ring oscillator. The simulation results and hardware results show that the designed ADPLL is efficient in terms of catching range, locking duration, frequency resolution with low power utilization, compared to many previous works. To improve the frequency resolution and reduce the process duration, further, ring oscillator is replaced by Bootstrapping based oscillator technique with the same detector and filters used in the ES-DPLL and the design named as (R2PES-DPLL). Bootstrapping technique reduces the locking duration and enhances the frequency newline newline newline newlineresolution. The proposed method is implemented in virtex families and the system performance is verified by hardware utilization, area usage, frequency, power consumption, phase noise analysis, etc. The modified method outputs the maximum frequency of 3.2GHz with reduction in locking duration of 0.01µs. R2PES-DPLL is best suited for IoT applications compare to ES-DPLL with respect to ADPLL efficiency parameters. newline