Investigations on statistical approaches for improved static timing analysis in vlsi circuits

Abstract

Developments in semiconductor industry show a huge increase in chip frequency and design complexity. Technology scaling helps to focus on performance improvement and solve design complexity issues. It also imposes design validation challenges. As technology shrinks to the nanometer level, the effect of process variations in integrated circuit is highly dominant. The process variations are not fully random in nature. Environmental variations are also prominent. Such variations affect the attributes like power, circuit delay. Timing is a crucial parameter associated to the delay which determines the speed of operation of a circuit. Timing Analysis is done by considering speed and accuracy as the major concerns. Statistical Timing Analysis (STA) is a method which analyzes all possible paths in a circuit and checks for timing violations but it avoids the functionality check. A static timing analyzer works based on the constraints fed to it. Also any types of variations are not taken into account by this method. Arrival time computation also gets affected due to the variations and hence statistical approaches are to be incorporated with them to sort this issue. Statistical Static Timing Analysis (SSTA) is capable of handling process variations and it acts a feasible solution to both timing and toggle rate computation. Calculation of arrival time of circuits using STA and SSTA can be performed in a similar manner but the latter yields a refined output. Probabilistic methods are applied to benefit this refinement. It provides set of outcomes rather than a single output. Hence the pessimistic nature of STA is proved. The aim of this work is to propose various methods to improve the accuracy and speed in toggle rate computation and timing analysis. A detailed comparison of STA and SSTA is performed with the basic entities as arrival time and computation time. Circuits are modelled as timing graphs having set of vertices and edges. The gates in the circuit represent the vertices and the gate delays by the edges. The timing graphs are traversed level by level using Breadth First Search (BFS) or by means of any other graph traversal algorithms. Path selection is an important task in SSTA as there are chances that the relevant paths might be missed in analysis. Path based method sums the wire and gate delays on the specific paths. It is a very simple approach but the paths of interest should be chosen before performing the analysis. Statistical MAX operation and convolution integration on each edge and fan-out of the gates is performed to achieve block based SSTA results. Artificial Neural Network model is also developed to verify the arrival time obtained using two timing engines. It is observed from the results that the absolute error obtained with ANN is 92% whereas with the conventional approach is 46% .Hence the reduction in absolute error with the proposed method is reduced by 2X. newline